This invention relates to integrated circuits, particularly to static random access memory (SRAM) devices, in either embedded form or stand alone (i.e. discrete) form.
Memory cells in SRAM devices store logical binary values (i.e. either a logical one or a logical zero). When a memory cell is selected by a word line during a read, the voltage on a latch in the memory cell begins to change the voltages on the bit lines attached to the memory cell (i.e. signal is developing on the bit lines). Because the signal on the bit lines is initially small, a certain amount of time must pass to allow the signal on the bit lines to grow larger. When the signal on the bit lines reaches a certain value, this value may be sensed by a sense amp. The sense amp increases the voltage found on the bit lines so that the signal may be transferred to another part of the SRAM.
When data is read from an SRAM memory cell and the time allowed for the signal on the bit lines to increase is too short, the sense amp may fail to amplify the correct logical value and an error occurs in the SRAM. When data is read from an SRAM memory cell and the time allowed for the signal on the bit lines to increase is too long, the sense amp properly amplifies the correct logical value. However, because the time allowed was long, the read access time of the SRAM increases. In order to keep the read access time as short as possible and read correct data, it is important to be able vary the amount of time allowed for the signal on the bit lines to develop. Further, it is important to test SRAMs to ensure the availability of sufficient read margin by varying the amount of time allowed for a signal to develop on the bit lines during a read of an SRAM memory cell.